The best Hacker News stories from Show from the past day
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Show HN: Pagecast – Publish Markdown/HTML Reports to Cloudflare Pages
I built this because I kept generating HTML/Markdown reports from Claude Code/Codex and needed a permanent share link instead of a localhost tunnel. Pagecast is a local CLI that publishes those files to your own Cloudflare Pages account.<p>It supports Markdown and HTML, stable URLs, renaming, republishing to the same URL, and watch mode for continuous updates to same file. It is MIT licensed.<p>The main design choice is that there is no hosted Pagecast account. It uses your Cloudflare account and deploys there directly and has claude code and codex integrations as skill/hooks.<p>Basically it can be used as a replacement for codex sites or claude artifacts
Show HN: Modeloop – From visual algorithms to microcontroller C code
Show HN: Metiq: a real time 3D globe for 100 public datasets
The concept for metiq.space came after playing Global Magnates with friends and realizing how fragmented live global data is. ships, aircraft, satellites, ports, weather, hazards, infrastructure, cyber, and public datasets all exist, but they usually live in separate tools and maps.<p>The goal was to build one interactive 3D globe where live public data could be visualized by latitude, longitude, and altitude. Surface data stays on the globe, while aircraft, satellites, and other above surface things can be represented in actual 3D space instead of being flattened onto a map.<p>The outcome is an interactive globe that showcases Earth, air, sea, space, cyber, defense, infrastructure, politics, and the list is continuously growing.<p>Majority of development right now is going into data filtering and deduping.
Show HN: Talos – Open-source WASM interpreter for Lean
At Cajal (YC W26) we’re excited to share Talos (<a href="https://github.com/cajal-technologies/talos" rel="nofollow">https://github.com/cajal-technologies/talos</a>), an open source framework for formal verification of WebAssembly modules in Lean.<p>AI is now writing tons of the code that gets pushed to production. As code generation gets cheaper, verification becomes the bottleneck. We believe in a future where every piece of software comes with a mathematical proof that it does what its author intended - in doing so, eliminating many classes of exploits. Talos is part of the foundation for that.<p>Talos provides a Wasm interpreter optimized for reasoning at the binary level, together with a weakest-precondition calculus layer for proving properties about programs. Because we reason directly about WebAssembly, any language with a Wasm backend is in scope: Rust, C++, Go, C, Swift, Kotlin, Zig, C#, and many more.<p>To make this possible, we use Lean: a programming language and theorem prover that lets you both write software and mathematically prove that it's correct - all in one system. That's what lets Talos double as both an executable interpreter and the formal object Lean reasons about. Lean also integrates with modern AI proving tools, discharging goals automatically via both proof search and direct evaluation.<p>To see Talos in action check out a proof for Stein's GCD algorithm, implemented in the popular Rust crate num-integer: <a href="https://github.com/cajal-technologies/talos/blob/main/programs/lean/Project/NumInteger/Spec.lean#L562-L588" rel="nofollow">https://github.com/cajal-technologies/talos/blob/main/progra...</a>.<p>Our roadmap:<p>- Full Wasm coverage by first passing the official W3C testsuite, then later verifying against SpecTec (formal Wasm spec)
- Arbitrary crate verification - any Rust crate that compiles to Wasm should be in scope
- Building our proof library codelib, to make verifying increasingly complex programs tractable<p>We would love to hear the community’s feedback on Talos and comments on the state of formal verification right now. Contributions are also welcome!
Show HN: 10x better performance from the Coding Harnesses with LLM-wiki
Show HN: Deconvolution – a Rust image deconvolution and restoration crate
I've been working on deconvolution, a comprehensive Rust image deconvolution and restoration library. Deconvolution implements 28 different image deconvolution/restoration methods which range from practical blur removal techniques to research-grade scientific imaging algorithms.<p>Features:<p>- Top-level functions use image::DynamicImage and return images<p>- Inverse filters, Wiener, Richardson-Lucy, constrained, proximal, Krylov, MLE restoration<p>- Blind Richardson-Lucy, blind maximum likelihood, parametric PSF estimation<p>- Kernel2D, Kernel3D, Transfer2D, Transfer3D, Blur2D/Blur3D<p>- Gaussian, motion, defocus, microscopy models, support utilities, PSF/OTF conversion<p>- Edge tapering, apodization, range normalization, NSR estimation<p>- Deterministic blur, noise, synthetic fixture generation<p>- ndarray support for 2D image arrays and 3D volume<p>this project is a WIP, of course:)
Show HN: Spin Lab
Hey HN, I built Spin Lab: a browser-based interactive explainer for table-tennis spin. It visualizes topspin/backspin, spin rate, ball trajectory, bounce behavior, and why the opponent’s return reacts the way it does. I built it because spin is central to table tennis, but most explanations are either too hand-wavy or too static.<p>Thanks Fable, we miss you
Show HN: We built an 8-bit CPU as 2nd year EE students
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs.<p>key features:
Custom 16-instruction Harvard ISA, 8-bit fixed
format, 4 general purpose registers<p>Hardwired control unit built entirely from AND/OR gate logic matrix<p>Dual-phase clocking to eliminate race conditions<p>Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer
Early-exit conditional branching that saves upto 25% cycles when conditions aren't met<p>Full design specification document with version control<p>Since this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers.
There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.<p>There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.<p>To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.<p>We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.<p>Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.<p>Please take a look at it at <a href="https://github.com/c0rRupT9/STEPLA-1" rel="nofollow">https://github.com/c0rRupT9/STEPLA-1</a><p>For future development I want to implement a RISC CPU using FPGA's and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion
<a href="https://tcfdiq.gumroad.com/l/zyyux" rel="nofollow">https://tcfdiq.gumroad.com/l/zyyux</a>
Thankyou!
Show HN: We built an 8-bit CPU as 2nd year EE students
Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs.<p>key features:
Custom 16-instruction Harvard ISA, 8-bit fixed
format, 4 general purpose registers<p>Hardwired control unit built entirely from AND/OR gate logic matrix<p>Dual-phase clocking to eliminate race conditions<p>Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer
Early-exit conditional branching that saves upto 25% cycles when conditions aren't met<p>Full design specification document with version control<p>Since this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers.
There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.<p>There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.<p>To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.<p>We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.<p>Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.<p>Please take a look at it at <a href="https://github.com/c0rRupT9/STEPLA-1" rel="nofollow">https://github.com/c0rRupT9/STEPLA-1</a><p>For future development I want to implement a RISC CPU using FPGA's and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion
<a href="https://tcfdiq.gumroad.com/l/zyyux" rel="nofollow">https://tcfdiq.gumroad.com/l/zyyux</a>
Thankyou!
Show HN: Gerrymandle - Daily puzzle game where you redraw electoral districts
Show HN: Gerrymandle - Daily puzzle game where you redraw electoral districts
Show HN: Are You in the Weights?
With more traffic moving off-web and into LLMs, I got curious about what traces we leave "in the weights". My design partner and I built a site in the past few weeks that checks recognition across frontier and small models. It queries many of them in parallel, clusters the responses, and tells you how strongly they recognize you. Happy to answer any questions here!
Show HN: Are You in the Weights?
With more traffic moving off-web and into LLMs, I got curious about what traces we leave "in the weights". My design partner and I built a site in the past few weeks that checks recognition across frontier and small models. It queries many of them in parallel, clusters the responses, and tells you how strongly they recognize you. Happy to answer any questions here!
Show HN: I built 184 free browser tools – PDF, image, dev, AI tasks, no upload
Show HN: cuTile Rust: Safe, data-race-free GPU kernels in Rust
Show HN: Capacitor Alarm Clock
I made an alarm clock that blows up capacitors to wake you up.<p>There are more details on the Github repo but it's made from an esp32-c3 as the microcontroller, with 3 capacitor slots. There are relays on each capacitor slot to put 15v reverse voltage on the capacitor, with 5.1 ohm resistors on each slot for current limiting in case the capacitor shorts out. I also chucked in an SSD1315 OLED to show the time and a menu to configure it, although there's a web UI as well. The esp32 also means you can fetch the time from NTP.<p>It also functions as a small heater since I used LDOs to step down 15v to 3.3v for the esp32, I was lazy and didn't use a buck converter circuit :)
Show HN: Capacitor Alarm Clock
I made an alarm clock that blows up capacitors to wake you up.<p>There are more details on the Github repo but it's made from an esp32-c3 as the microcontroller, with 3 capacitor slots. There are relays on each capacitor slot to put 15v reverse voltage on the capacitor, with 5.1 ohm resistors on each slot for current limiting in case the capacitor shorts out. I also chucked in an SSD1315 OLED to show the time and a menu to configure it, although there's a web UI as well. The esp32 also means you can fetch the time from NTP.<p>It also functions as a small heater since I used LDOs to step down 15v to 3.3v for the esp32, I was lazy and didn't use a buck converter circuit :)
Show HN: Capacitor Alarm Clock
I made an alarm clock that blows up capacitors to wake you up.<p>There are more details on the Github repo but it's made from an esp32-c3 as the microcontroller, with 3 capacitor slots. There are relays on each capacitor slot to put 15v reverse voltage on the capacitor, with 5.1 ohm resistors on each slot for current limiting in case the capacitor shorts out. I also chucked in an SSD1315 OLED to show the time and a menu to configure it, although there's a web UI as well. The esp32 also means you can fetch the time from NTP.<p>It also functions as a small heater since I used LDOs to step down 15v to 3.3v for the esp32, I was lazy and didn't use a buck converter circuit :)
Show HN: Inkwash, a watercolor sketching app and explanation
I've made a drawing app based on my physical sketching practice, using fluid sim and some shader tricks to mimic watercolor-style ink washes. Best used on iPad or with a drawing tablet. The linked article shows how the core engine works, with plenty of little interactive demos. It was fun to make, sharing in hopes others find it fun too :)
Show HN: Inkwash, a watercolor sketching app and explanation
I've made a drawing app based on my physical sketching practice, using fluid sim and some shader tricks to mimic watercolor-style ink washes. Best used on iPad or with a drawing tablet. The linked article shows how the core engine works, with plenty of little interactive demos. It was fun to make, sharing in hopes others find it fun too :)